1. Technical Field
Many electronic products today incorporate one or more memory arrays. These electronic products having memory arrays further include address and data registers and associated combinatorial and/or sequential logic circuitry. These memory arrays are deemed "embedded" if the memory arrays are not directly accessible, either in whole or in part from the input or output lines to the product. This present invention is directed to random pattern testing of such electronic products having embedded arrays. Electronic products designs utilizing "boundary scan circuits" for embedded arrays refer to design methods having sets of shift register latches which facilitates a logical separation between associated logic and embedded arrays. This logical separation facilitates independent testing of the associated logic and the embedded array for which a variety of test approaches have proven to be effective. More particularly, the present invention is directed to testing electronic products based on one or more embedded arrays not having boundary scan circuits at their inputs and outputs.
The electronic product designs which do not employ shift register latches for boundary scan isolation is the focus of this present invention. Unless otherwise noted, all the citations in this present disclosure in reference to embedded arrays are based on electronic designs wherein one or more embedded arrays do not have boundary scan isolation circuitry at their inputs and outputs.
The need for improved testing methods in integrated circuit products has grown with increased packaging density. The cost effectiveness of testing methods is the result of many distinct factors. One factor in testing methods includes the time for performing a test, wherein an increase in testing time translates to an increase in manufacturing time, which in turn translates to an increase in cost. Another factor in testing methods includes a range or extent of test coverage, that is, to what extent does the test methodology exercise every component, and test every interconnection. Still another aspect of testing methods includes an ability not only to catch a fault, but also, an ability to determine at what location the fault occurred. In product failure analysis, it is this ability to find the location of the fault that guides the manufacturing process to problem correction. For example, during failure analysis related to a specific location, a corrective action for a faulty connector or a solder bridge is seen to be different than a corrective action due to damage from microscopic debris, and different still, than a corrective action for a design error. Still another factor in integrated circuit products testing is the cost associated with adding additional hardware, specifically the cost of components and interconnections, necessary to enable a particular testing method to be carried out. The self-evident conclusion is to minimize the addition of hardware whenever possible. Manufacturers must therefore balance the considerations of test time, test coverage, test hardware expense, and an ability to establish a specific location of a test failure when improving upon current methods of electronic product testing.
For products having embedded arrays without boundary scan circuits at their inputs and outputs, typical logic testing methods exist. In order to review a typical logic testing method, let us first consider the common components of a typical electronic product with embedded arrays. A typical electronic product comprises embedded arrays having memory address registers, memory data registers, and associated memory logic. "Primary inputs" and "primary outputs" are the physical pins or connectors through which the electronic product receives and transmits information to external devices. The embedded arrays of the electronic product further include data inputs and data outputs. The associated memory logic is typically combinatorial and can be further divided into two types, associated memory pre-logic and associated memory post-logic. The associated memory pre-logic connects primary inputs of the electronic product to the data inputs of the embedded arrays while the associated memory post-logic connects the data outputs of the embedded arrays to primary outputs. In addition, the associated memory logic is often accompanied by feed-around logic that connect memory pre-logic circuits with memory post-logic circuits independently of the embedded array. More particularly, feed-around logic circuits connect to post-logic circuits as do the data outputs of the embedded array. Post-logic circuits produce output strings that are channeled out through the primary outputs of the electronic product. The output strings are collected by a signature register connected to the primary output for failure detection. For the present invention, the typical logic circuit testing methodology for electronic products having embedded arrays focuses on testing both the embedded memory array and its associated logic.
The typical logic testing method for products having embedded arrays can be broken down into a few distinct steps. The steps begin with the initialization of all the embedded arrays to random values. As used herein and in the appended claims, "random" refers both to random and quasi-random processes. Next, random read tests are performed while random data is applied to the primary inputs of the associated pre-logic circuits. Continuing further, the outputs of the associated pre-logic circuits are connected through the feed-around logic to the post-logic circuits. During the random read portion of the test, the random initialized values are read into the post-logic via the embedded arrays while signals coming from the feed-around logic are fed into post-logic circuits. Post-logic circuits produce output pattern sequences which output on the primary outputs of the electronic product. The output pattern sequences are collected by a signature register. In a separate external apparatus (not shown), signature analysis is performed on the output pattern sequences collected in the signature register. If during a signature analysis a deviation from an expected pattern is found, then a problem is flagged. In order to gain higher statistical test confidence, the previous random read step is repeated. Each time the random read step is repeated, it is usually necessary to go through the procedure to rewrite random values into the embedded arrays. Repeating the rewrite step ensures that fresh random values have been stored, thereby enhancing a probability of detecting pattern resistant faults. In addition, all throughout this testing phase, embedded arrays are operated in a read only mode. The advantage gained by using the embedded arrays in only the read mode during logic circuit testing is that there is no need to use a sequential fault simulator that is normally needed to track the past history of the inputs of the electronic product. Instead, whenever a fault is detected, all the information needed to diagnose the fault exists in the electronic product. More specifically, the random data values that triggered that fault lie at the primary inputs of the electronic product and in the random data information currently stored in the embedded arrays. There is no need to look for any data that was stored in the embedded array in the past and that did not exist at the detection time of the fault.
The typical testing method for electronic products having embedded arrays, however, has numerous shortcomings. First, the initialization of the embedded memory array is a very time consuming effort. It is time consuming because the initialization of all the embedded arrays with random data requires long random pattern sequences to be applied to the primary inputs of the electronic product. The generation and application of long patterns is a comparatively slow operation. Secondly, in order to have an effective test, it is necessary to frequently deliver fresh random data into the embedded array. With every fresh random data delivery, the read test has to be repeated to determine if it can capture any as yet undetected faults.
The present invention is an improved method to test and diagnose electronic products having embedded arrays wherein one or more embedded arrays do not have boundary scan circuits at their inputs and outputs.
2. Background Art
The following documents relate to various methods for testing electronic products having embedded arrays wherein one or more embedded arrays do not have boundary scan circuits at their inputs and outputs.
U.S. Pat. No. 5,062,109 issued 29 Oct. 1991 to Ohshima et al. for "Memory Tester" appears to disclose a memory tester in which data is read out from the memory being tested at an address specified by a pattern generator. The data read out is compared with an expected value. The result of the comparison is written into a failure analysis memory at the address corresponding to that of the memory being tested.
U.S. Pat. No. 4,680,761 issued 14 Jul. 1987 to Burkness for "Self Diagnostic Cyclic Analysis Testing System (CATS) for LSI/VLSI" appears to disclose a testing system wherein a logic device of the product under test is isolated and reconfigured to simulate a non-linear binary sequence generator. The memory elements associated with the logic device are preset to a predetermined value and the logic device is clocked for a given number of steps to define a testing cycle. The settings of the memory elements are compared with the known settings, and a fault condition is indicated when the settings differ from the known settings.
U.S. Pat. No. 4,481,627 issued 6 Nov. 1984 to Beauchesne et al. for "Embedded Memory Testing Method And Apparatus" appears to disclose a method of testing products having embedded arrays through electrical isolation of the combinatorial logic components and the memory array components using high impedance states. This means of electrical isolation enables independent testing of the combinatorial logic components and the memory array components.
U.S. Pat. No. 3,961,252 issued 1 Jun. 1976 to Eichelberger et al. for "Testing Embedded Arrays" appears to disclose a method of testing products having embedded arrays wherein the address registers and the data registers are converted to counters by the addition of an EXCLUSIVE OR circuit connected on two or more positions of the data registers. The address and data registers are stepped through all their states, The data register counter outputs are then compared with the array outputs, thereby enabling verification of address selection as well as enabling verification of the reading or writing operations at each of the embedded array storage locations.
U.S. Pat. No. 3,751,649 issued 7 Aug. 1973 to Hart for "Memory System Exerciser" appears to disclose a memory tester in which stored program instructions govern the data generation, the memory addressing, the read/write operation, and the comparison of data or address values.
IBM Technical Disclosure Bulletin, Vol. 33 No. 1A June 1990 "Method To Access Individual Embedded Arrays via Tester Or External Support Processor In A Way Compatible With Built-In-Self-Test" by Bakoglu et al. appears to disclose a method to read and write individual embedded arrays without disturbing the contents of the other arrays.
IBM Technical Disclosure Bulletin, Vol. 20 No. 6 November 1977 "Random Test Patterns To Logic Surrounding Embedded Arrays" by Goel et al. appears to disclose a method to reduce the testing costs of logic with embedded arrays by determining which test input patterns set will cause a READ/WRITE operation. This set of predetermined inputs reduces the number of input strings which must be applied.